
VIA FAQ




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The following is a selection of questions frequently asked to VIA Field Application Engineering and Design Engineering teams. 

VIA encourages you to submit any technical questions you may have so we can regularly update this list.
Please contact yclin@via.com.tw VIA FAE, with questions.
   

How does IDE operation differ when running with and without the Via device drivers?
 
The driver has adjustabler parameters. When the system runs with the drivers, the parameters can be adjusted in order to allow system to operate to maximum performance. These parameters include timing control, set-up time access time and numerous others. While operating without driver, the system slows down during hardisk access.



What advantages does Apollo 580VP offer compared to Apollo Master 570M?

Apollo 580VP introduces numerous features and increased performance when compared to the Apollo Master 570M. As with 570M, Apollo VP features BEDO. VP580 features a number of cutting-edge technologies not found on the 570M, including Unified Memory Archietecture (UMA), Universal Serial Bus (USB), and SDRAM.

What are the technical details for VIA's UMA support?

VIA supports UMA with a standard video/GUI controller based on either two-pin or three-pin RE/GNAT protocols. The system includes arbitration logic with levels of priorities, programmable synchronous or asynchronous interface with guarantee grant latency.   The chip set is also responsible for DRAM refresh, direct frame buffer access, frame buffer memory mapping and arbitration control. With the intelligent arbitration, multiple deep buffer  to maximize latency sensitivity and DRAM utilization , and zero wait state bursting capabilities of BEDO and SDRAM, VIA's UMA system can utilize DRAM most efficiently and deliver optimum performance for shared frame application performance.  



What is the difference between ATA and ATAPI?

The difference is that the  ATAPI standard can support CD-ROM and tape drives. All devices compatible with the ATA standard are compatible , with the ATAPI standard. 



What are the price/performance options between PBSRAM and asynchronous SRAM?

PBSRAM offers better performance than asynnch SRAM (if your concern is performance). Presently the price differential between the two is minimal. 



Does the Apollo VP's asynchronous SRAM & PBSRAM operate at the same time?

No. On the mainboard there is a connection between asynch SRAM and PBSRAM,but only one device can be enabled at a time.    



What is VRM?

VRM stands for voltage Regulator Module to  support the P55C's 2.5v (3.3 I/O) operation voltage. The VRM has a 30-pin connector configured as a 2x15 matrix and converts 5 volts to the proper voltage and current for the processor.    



What is full scatter and gather capability?

The scatter and gather mechanism allows for the large transfer of blocks of data to and from memory. This function optimizes interrupts and CPU intervention.



How does the Apollo 570M utilize snoop ahead?

After the 570M's controller generates a snoop ahead, the controller may continue burst operation without waiting one clock cycle for the CPU response. 



What is concurrent operation of CPU/Cache & PCI/DRAM?

In a typical  system,  the operation of PCI Master access  to the bus is a bottleneck. When the PCI Master issues a REQ#, the PCI arbitrator will   follow the arbitration protocol and grant to the PCI Master. The PCI Master can then access slave devices on the PCI bus. During this sequence, the CPU and CPU bus are not interfered with. Consequently, the CPU and CPU bus are left free to process other operations concurrently with the PCI master operations and the bottleneck is bypassed.



Does the 580VP support Unified Memory Architecture (UMA)? 

The 580 VP contains core-logic to support UMA, with video/GUI products from major vendors. Multiple deep FIFOs (thirty-two double words) are included between multiple data paths to allow efficient concurrent operation and DRAM utilization.



What is NA pipeline?

NA pipeline describes a process in which the CPU executes a bus cycle, has not yet finished the cycle, and recieves another bus cycle address signal. In this mode, the CPU can  execute instructions without any wait state or clock delay.       



Does the cache operation mode of the CPU have to be the same as the L2 cache?

They both operate at write-back or write-through if  the  controller & CPU support these two modes . The operation mode cannot be the same for CPU and cache controller. 



Can you describe the 570M's master mode IDE controller?

The 570M features an integrated  Master Mode IDE controller that supports dual channel/four device EIDE bus. It can  support mode-3 and mode-4 transfer rates and a CD-ROM drive.



How fast can the 570M with L2 cache operate with Burst Synchronous SRAM?

If equipped with L2 cache using burst synchronous SRAM, 3-1-1-1 timing can be achieved for both read and, write transactions at 66 MHz. For standard SRAMs, 3-2-2-2 and 4--2-2-2  timing  can be achieved for interlevered read and write transactions at 66MHz.



What purpose does the 570M's DRAM post write buffer serve? 

With the 570M, four levels of DRAM support post write buffer to optimize the performance of the L2 cache write miss and non-cacheable write operations. The CPU writes data to the fast buffer and then terminates the cycle without any wait states. 






Please contact  mail to:sdavidson@via.com.tw" Webmaster with inquiries.   



